Design a true single-phase clocked (TSPC) register with a ?????????? input: when the RESET signal is 1, the output of the register will be reset to 0, irrespective of the clock signal.
engineering
Description
Complete the following design tasks in the 0.18μm CMOS technology provided.
Task 1: Design a true single-phase clocked (TSPC) register with a ?????????? input: when the RESET signal is 1, the output of the register will be reset to 0, irrespective of the clock signal. The register updates its output on the rising edge of its clock input CLK when RESET is 0. (The design is now given in the next page.)
Task 2: Design a 4-bit adder. (10%)
Task 3: Design a 4-bit counter. The counter needs to increase its output by 1, starting from 0, on a rising edge of the CLK signal. Let us denote the output of the counter as a 4-bit binary number ??. The counter needs to reset its output to ‘0000’ when ?? + ?? = ′1111′, where B is an arbitrary 4-bit binary number. Try ?? = ′1010′ and ′0101′ to demonstrate your design. (10%)
Requirements: -
You can use a supply equal to or less than 1.8V.
- The frequency of the CLK signal is 10MHz. You can use a voltage source to generate an ideal square waveform in your simulations.
- You are advised to apply the sub-circuit function in the WinSpice for a modular design.
