Description

Given a memory and an I/O device on a bus as shown below: 64 bit wide bus, synchronous, 50MHz clock ============================================================== | | address and | two 32-bit data address and | two 32-bit data word count | words sent word count | words received received in | in one clock sent in one | in one clock one clock | clock | | | +-----+-----+-----+-----+ +-----+-----+ | | | | |Registers | I/O device| +-----+-----+-----+-----+ | receiving | | RAM memory that is | | word-count| | four 32-bit words wide| | words of | | and has output | | data | | registers for four | +-----------+ | words | +-----------------------+ The system operates by the I/O device sending an address and word count to the memory. The memory uses the address to start a memory access that brings four 32-bit words into the memory output registers. In parallel, [the memory starts the access of the next four words] and [sends two words on the bus, then two more words on the bus, then a bus idle, then another bus idle]. Thus, the bus actions are overlapped with the next memory access. Note that the bus may be used by other devices between these four clock operations on the bus. The memory access is non uniform. Upon receiving an address, the first memory access takes longer than the following memory accesses. This happens in some memories due to the extra time to charge word or block select lines. Once started with an address and word count, the memory puts data on the bus until the word count is satisfied. For this exercise the first memory access requires 5 clocks and each additional memory access in the same transaction requires 4 clocks. A bus transaction starts with the sending of an address and word count. The transaction ends when the last word and two idles are received by the I/O device. The transaction time does not include the one clock to send the address and word count. Bandwidth is measured in megabytes per second. The address and word count are not included in the byte count and not included in the time. For the I/O device to get 512 words when the I/O device uses 4 as the word count. (512 words is 2048 bytes) a) Compute the total time from after receipt of the address to the end of the last transaction. b) Compute the transactions per second. c) Compute the bandwidth. For the I/O device to get 512 words when the I/O device uses 32 as the word count. d) Compute the total time from after receipt of the address to the end of the last transaction. e) Compute the transactions per second. f) Compute the bandwidth. Show your work as formulas or as tables. Be consistent. Use either clock counts or nanoseconds. Obviously a 50MHz clock uses 20 nanoseconds per clock.